参考文献
[1] Kelin J.Kuhn, Mark Y.Liu, Harold Kennel.Technology Options for 22nm and Beyond.Proc.of 10th International Workshop on Junction Technology(IWJT), IEEE,2010.
[2] N.Mohta, S.E.Thompson.Strained Si-The Next Vector to Extend Moore's Law.IEEE Circuits and Devices Magazine,2005(21):18.
[3] T.Komoda, A.Oishi, T.Sanuki, et al.Mobility Improvement for 45nm Node by Combination of Optimized Stress Control and Channel Orientation Design.IEDM,2004.
[4] K.Ikeda, et al.Integration Strategy of Embedded SiGe S/D CMOS from viewpoint of performance and cost for 45nm node and beyond.IEDM,2008.
[5] M.Bargallo Gonzalez, et al.Analysis of the Pre-epi Bake Conditions on the Defect Creation in Recessed Si1-xGexS/D Junctions.ECS Fall Meeting,2007.
[6] K.Mistry, et al.A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers,193nm Dry Patterning, and 100% Pb-free Packaging.IEDM,2007.
[7] N.Tamura, et al.Embedded Silicon Germanium(eSiGe)technologies for 45nm nodes and beyond. IEDM,2008.
[8] J.-P.Han, et al.Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices.IEDM,2006.
[9] Z.Luo, et al.Design of High Performance PFETs with Strained Si Channel and Laser Anneal.IEDM, 2005.
[10] M.Kolahdouz, et al.Comprehensive Evaluation and Study of Pattern Dependency Behavior in Selective Epitaxial Growth of B-Doped SiGe Layers.IEEE Trans.Nanotechnology,2009(8):291.
[11] S.Flachowsky, et al.Detailed Simulation Study of Embedded SiGe and Si:C S/D Stressors in Nano Scaled SOI MOSFETs.Proc.International Workshop on INSIGHT in Semiconductor Device Fabrication, Metrology and Modeling,2009.
[12] M.Bauer, D.Weeks, Y.Zhang, V.Machkaoutsan.Tensile strained selective silicon carbon alloys for recessed source drain areas of devices.ECS Trans.,2006,3(7):187.
[13] L.Peters.Strained Silicon:Essential for 45nm.Semiconductor International,2007.
[14] P.Verheyen, et al.Strain Enhanced nMOS Using In Situ Doped Embedded Si1.xCx S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process.IEEE Electron Dev.Lett.,2008,29(11):1206.
[15] K.W.Ang.Performance Enhancement in Uniaxial Strained Silicon-on-Insulator N-MOSFETs Featuring Silicon-Carbon Source/Drain Regions.IEEE Trans.Electron Dev.2007,54(11):2910.
[16] B.Yang, et al.High-performance nMOSFET with in-situ Phosphorus-doped embedded Si:C(ISPD eSi:C)source-drain stressor.IEDM,2008.
[17] M.Nishikawa, et al.Successful Integration Scheme of Cost Effective Dual Embedded Stressor Featuring Carbon Implant and Solid Phase Epitaxy for High Performance CMOS.VTSA,2009.
[18] S.S.Chung, et al.Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C.VLSI Tech.Digest,2009.
[19] Y.Liu, et al.Strained Si Channel MOSFETs with Embedded Silicon Carbon Formed by Solid Phase Epitaxy.VLSI Tech.Digest,2007.
[20] H.Maynard, et al.Enhancing Tensile Stress and Source/Drain Activation with Innovation in Ion Implant and Millisecond Laser Spike Annealing.16th IEEE Int.Conf.on Advanced Thermal Processing of Semiconductors-RTP,2008.
[21] C.H.Chen et al.Stress Memorization Technique(SMT)by Selectively Strained-Nitride Capping for Sub-65nm High-Performance Strained-Si Device Application.VLSI Tech.Digest,2004.
[22] K.Ota et al.Novel Locally Strained Channel Technique for High Performance 55nm CMOS.IEDM, 2002.
[23] A.Wei et al.Multiple Stress Memorization in Advanced SOI CDMOS Technologies.VLSI Tech. Digest,2007.
[24] A.Eiho et al.Management of Power and Performance with Stress Memorization Technique for 45nm CMOS.VLSI Tech.Digest,2007.
[25] T.Miyashita et al.Physical and Electrical Analysis of the Stress Memorization Technique(SMT)using Ploy-Gates and its Optimization for Beyond 45-nm High-Performance Applications. IEDM,2008.
[26] C.Ortolland.et al.Stress Memorization Technique-Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process.IEEE Trans.Electron Dev.,2009,56:1690.
[27] E.Morifuji, et al.Optimization of Stress Memorization Technique for 45nm Complementary Meta-l Oxide-Semiconductor Technology.Jap.J Appl.Phys.,2009,58:031203.
[28] C.Ortolland et al.Stress Memorization Technique(SMT)Optimization for 45nm CMOS.VLSI Tech.Digest,2006.
[29] H.S.Yang, et al.Dual Stress Liner for High Performance sub-45 Gate Length SOI CMOS Manufacturing.IEDM,2004.
[30] E.Leobandung.High Performance 65nm SOI Technology with Dual Stress Liner and low capacitance SRAM cell.VLSI Tech.Digest,2005.
[31] S.Fang, et al.Process Induced Stress for CMOS Performance Improvement.ICSICT,2006.
[32] P.Grudowski, et al.1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations.VLSI Tech.Digest,2006.
[33] J.Yuan, et al.A 45nm low cost low power platform by using integrated dua-l stress-liner technology.VLSI Tech.Digest,2006.
[34] K.Uejima, et al.Highly Efficient Stress Transfer Techniques in Dual Stress Liner CMOS Integration.VLSI Tech.Digest,2007.
[35] S.Mayuzumi.High-Performance Metal/High-k n-and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on(100)Substrates.IEEE Trans.Electron Dev., 2009,56:620.
[36] M.Belyansky, et al.Methods of producing plasma enhanced chemical vapor deposition silicon nitride thin films with high compressive and tensile stress.J.Vac.Sci.Tech.2008,26:517.
[37] E.P.van de Ven, I-W.Connick, A.S.Harrus.Advantages of Dual Frequency PECVD for Deposition of ILD and Passivation Films.VMIC,1990.
[38] J.Wang, et al.Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process and high-performance pFETs.VLSI Tech.Digest,2007.
[39] C.Auth, et al.45nm High-k+Metal Gate Strain-Enhanced Transistors.VLSI Tech.Digest,2008.
[40] X.Chen, et al.Stress Proximity Technique for Performance Improvement with Dual Stress Liner at 45nm Technology and Beyond.VLSI Tech.Digest,2006.
[41] S.Fang, et al.Process Induced Stress for CMOS Performance Improvement.ICSICT,2006.
[42] J.Yuan, et al.A 45nm low cost low power platform by using integrated dual-stress-liner technology.VLSI Tech.Digest,2006.